In recent years, the opening diameter of a contact hole for achieving interlayer conduction in semiconductor devices is microminiaturized as the semiconductor devices are highly integrated and miniaturized. Therefore, it has become increasingly difficult to perform an etching process for contact hole formation. Consequently, inspection and measurement processes for determining whether the contact hole is good have become increasingly important for process development.
A known technology for making it easy to observe a contact hole with a scanning electron microscope is disclosed, for instance, in Patent Document 1. This technology (hereinafter referred to as the precharge technology or the preliminary charge technology) makes it possible to observe the contact hole by preliminarily irradiating a sample with an electron beam before inspection and measurement to form a desired charge in advance and then irradiating the sample with an electron beam at the time of image acquisition to extract electrons from the contact hole. To positively charge the sample during a precharge, it is necessary to ensure that a secondary electron generation efficiency δ, which is the ratio of a secondary electron generation amount to a primary electron beam irradiation amount, is higher than 1. The secondary electron generation efficiency δ has a correlation with a primary electron beam irradiation potential. Patent Document 1 describes a technology for performing a precharge process under conditions different from those for contact hole observation and observing the contact hole without decreasing a charge efficiency and without increasing the length of processing time.
When the above-mentioned precharge process is performed, an electron beam may drift due to a nonuniform charge. Patent Document 2 describes a technology for using a larger electron beam diameter for charge formation than an electron beam diameter for image acquisition.
In addition, a three-dimensional integrated memory device is known as a next-generation device that inhibits the cost of development and manufacture from being unduly increased by high integration and miniaturization of semiconductor memory devices. This next-generation device is described, for instance, in Non-Patent Document 1.